In recent years, with higher degrees of integration and higher performance of semiconductor integrated circuits (LSI), new microprocessing technologies have been developed. In particular, to achieve a faster speed of LSI, there has been a growing trend recently to replace the conventional wire material of aluminum (Al) alloys with copper (Cu) or Cu alloys (hereinafter, called Cu together) having low resistance. Since it is difficult to apply the dry etching method, which is used for forming an Al alloy wire, to Cu for microprocessing, the so-called damascene process is mainly adopted for Cu, in which a Cu film is deposited onto a dielectric film to which groove processing has been provided and then the Cu film is removed except in portions where the Cu film is embedded in a groove by chemical mechanical polishing (CMP) to form an embedded wire. The Cu film is generally formed, after forming a thin seed layer by a sputtering process or the like, into a laminated film having a thickness of several hundred nanometers by the electro-plating method.
Further, when forming a multilayer Cu wire, particularly a wire formation method called the dual damascene structure can also be used. According to this method, a dielectric film is deposited onto a lower layer wire and predetermined via holes and trenches for upper layer wire are formed, and then Cu to be a wire material is embedded in the via holes and trenches simultaneously and further unnecessary Cu on the upper layer is removed by CMP for planarization to form an embedded wire.
Recently, the use of a low dielectric constant film (low-k film) having a low relative dielectric constant as an inter-level dielectric is studied. That is, an attempt is made to reduce parasitic capacitance between wires by using a low-k film whose relative dielectric constant k is 3 or less, instead of silicon oxide (SiO2) whose relative dielectric constant k is about 4.1.
Currently, wiring layers are laminated into a multilayer interconnection by classifying wiring layers into wiring layer groups having a common minimum wire width. A multilayer interconnection is formed, for example, as a local layer on a device layer, an intermediate layer group on the local layer, a semi-global layer group formed thereon, and a global layer group formed thereon. The relative dielectric constant k of a main inter-level dielectric constituting each wiring layer in these groups is formed to have substantially the same value because wiring rules are common. Since the relative dielectric constant k needs to be made smaller with the group down the multilayer interconnection hierarchy, a low dielectric constant material is used, for example, for the semi-global layer group or so and below.
Generally, mechanical strength of low dielectric constant materials, particularly low dielectric constant films whose k is 3 or less, is weaker than that of non-low dielectric constant films. In addition, there is a tendency that mechanical strength of materials becomes weaker with decreasing dielectric constant. Using such low-k materials and lower mechanical strength of such materials may cause a peeling of multilayer interconnection. This problem is more likely to arise particularly, among multilayer interconnection manufacturing processes, in the CMP process in which a mechanical force is applied, a process in which a wafer is scribed to a chip shape, a process of fixing using a resin, and when a wafer is evaluated by probing.
Here, a technology of configuring dielectric films constituting each wiring layer of multilayer interconnection in such a way that strength/weakness of mechanical strength of the dielectric films alternates in the lamination direction so as not to cause defects such as film peeling and deformation in a multilayer interconnection structure is disclosed, for example, Japanese Patent Application Publication No. 2006-216746. However, according to such a technology in JP-2006-216746, mechanical strength is improved by a reinforcing film whose relative dielectric constant is large and thus, strength of the relative dielectric constant alternates from layer to layer. Therefore, originally desired wire performance is hardly obtainable from layers having a large relative dielectric constant.